Mercurial > hg > nginx-quic
view src/os/unix/ngx_gcc_atomic_ppc.h @ 6982:ac9b1df5b246
SSL: disabled renegotiation detection in client mode.
CVE-2009-3555 is no longer relevant and mitigated by the renegotiation
info extension (secure renegotiation). On the other hand, unexpected
renegotiation still introduces potential security risks, and hence we do
not allow renegotiation on the server side, as we never request renegotiation.
On the client side the situation is different though. There are backends
which explicitly request renegotiation, and disabled renegotiation
introduces interoperability problems. This change allows renegotiation
on the client side, and fixes interoperability problems as observed with
such backends (ticket #872).
Additionally, with TLSv1.3 the SSL_CB_HANDSHAKE_START flag is currently set
by OpenSSL when receiving a NewSessionTicket message, and was detected by
nginx as a renegotiation attempt. This looks like a bug in OpenSSL, though
this change also allows better interoperability till the problem is fixed.
author | Sergey Kandaurov <pluknet@nginx.com> |
---|---|
date | Tue, 18 Apr 2017 16:08:44 +0300 |
parents | d620f497c50f |
children |
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/* * Copyright (C) Igor Sysoev * Copyright (C) Nginx, Inc. */ /* * The ppc assembler treats ";" as comment, so we have to use "\n". * The minus in "bne-" is a hint for the branch prediction unit that * this branch is unlikely to be taken. * The "1b" means the nearest backward label "1" and the "1f" means * the nearest forward label "1". * * The "b" means that the base registers can be used only, i.e. * any register except r0. The r0 register always has a zero value and * could not be used in "addi r0, r0, 1". * The "=&b" means that no input registers can be used. * * "sync" read and write barriers * "isync" read barrier, is faster than "sync" * "eieio" write barrier, is faster than "sync" * "lwsync" write barrier, is faster than "eieio" on ppc64 */ #if (NGX_PTR_SIZE == 8) static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " li %0, 0 \n" /* preset "0" to "res" */ " lwsync \n" /* write barrier */ "1: \n" " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ /* and store reservation */ " cmpd %1, %3 \n" /* compare "temp" and "old" */ " bne- 2f \n" /* not equal */ " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ /* is not cleared */ " bne- 1b \n" /* the reservation was cleared */ " isync \n" /* read barrier */ " li %0, 1 \n" /* set "1" to "res" */ "2: \n" : "=&b" (res), "=&b" (temp) : "b" (lock), "b" (old), "b" (set) : "cc", "memory"); return res; } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " lwsync \n" /* write barrier */ "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ /* and store reservation */ " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ /* is not cleared */ " bne- 1b \n" /* try again if reservation was cleared */ " isync \n" /* read barrier */ : "=&b" (res), "=&b" (temp) : "b" (value), "b" (add) : "cc", "memory"); return res; } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ("isync \n lwsync \n" ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #else static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " li %0, 0 \n" /* preset "0" to "res" */ " eieio \n" /* write barrier */ "1: \n" " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ /* and store reservation */ " cmpw %1, %3 \n" /* compare "temp" and "old" */ " bne- 2f \n" /* not equal */ " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ /* is not cleared */ " bne- 1b \n" /* the reservation was cleared */ " isync \n" /* read barrier */ " li %0, 1 \n" /* set "1" to "res" */ "2: \n" : "=&b" (res), "=&b" (temp) : "b" (lock), "b" (old), "b" (set) : "cc", "memory"); return res; } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " eieio \n" /* write barrier */ "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ /* and store reservation */ " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ /* is not cleared */ " bne- 1b \n" /* try again if reservation was cleared */ " isync \n" /* read barrier */ : "=&b" (res), "=&b" (temp) : "b" (value), "b" (add) : "cc", "memory"); return res; } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ("isync \n eieio \n" ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #endif #define ngx_cpu_pause()