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110
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1
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2 /*
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3 * Copyright (C) Igor Sysoev
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4 */
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5
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6
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7 /*
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8 * "casa [r1] 0x80, r2, r0" and
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9 * "casxa [r1] 0x80, r2, r0" do the following:
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10 *
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11 * if ([r1] == r2) {
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12 * swap(r0, [r1]);
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13 * } else {
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14 * r0 = [r1];
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15 * }
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16 *
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17 * so "r0 == r2" means that the operation was successfull.
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18 *
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19 *
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20 * The "r" means the general register.
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21 * The "+r" means the general register used for both input and output.
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22 */
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23
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24
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25 #if (NGX_PTR_SIZE == 4)
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26 #define NGX_CASA "casa"
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27 #else
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28 #define NGX_CASA "casxa"
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29 #endif
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30
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31
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32 static ngx_inline ngx_atomic_uint_t
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33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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34 ngx_atomic_uint_t set)
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35 {
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36 __asm__ volatile (
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37
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38 NGX_CASA " [%1] 0x80, %2, %0"
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39
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40 : "+r" (set) : "r" (lock), "r" (old) : "memory");
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41
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42 return (set == old);
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126
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43 }
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110
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44
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45
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46 static ngx_inline ngx_atomic_int_t
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47 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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48 {
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49 ngx_atomic_uint_t old, res;
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50
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51 old = *value;
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52
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53 for ( ;; ) {
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54
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55 res = old + add;
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56
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57 __asm__ volatile (
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58
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59 NGX_CASA " [%1] 0x80, %2, %0"
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60
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61 : "+r" (res) : "r" (value), "r" (old) : "memory");
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62
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63 if (res == old) {
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64 return res;
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65 }
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66
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67 old = res;
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68 }
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69 }
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112
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70
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71
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72 #if (NGX_SMP)
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73 #define ngx_memory_barrier() \
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74 __asm__ volatile ( \
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75 "membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" \
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76 ::: "memory")
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77 #else
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78 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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79 #endif
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160
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80
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81 #define ngx_cpu_pause()
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