Mercurial > hg > nginx-vendor-0-5
view src/core/ngx_cpuinfo.c @ 326:f70f2f565fe0 NGINX_0_5_33
nginx 0.5.33
*) Change: now by default the "echo" SSI command uses entity encoding.
*) Feature: the "encoding" parameter in the "echo" SSI command.
*) Change: mail proxy was split on three modules: pop3, imap and smtp.
*) Feature: the --without-mail_pop3_module, --without-mail_imap_module,
and --without-mail_smtp_module configuration parameters.
*) Feature: the "smtp_greeting_delay" and "smtp_client_buffer"
directives of the ngx_mail_smtp_module.
*) Feature: the "server_name" and "valid_referers" directives support
regular expressions.
*) Feature: the "server_name", "map", and "valid_referers" directives
support the "www.example.*" wildcards.
*) Bugfix: sub_filter did not work with empty substitution.
*) Bugfix: in sub_filter parsing.
*) Bugfix: a worker process may got caught in an endless loop, if the
memcached was used.
*) Bugfix: nginx supported low case only "close" and "keep-alive"
values in the "Connection" request header line; bug appeared in
0.5.32.
*) Bugfix: nginx could not start on Solaris if the shared PCRE library
located in non-standard place was used.
author | Igor Sysoev <http://sysoev.ru> |
---|---|
date | Wed, 07 Nov 2007 00:00:00 +0300 |
parents | d2ae1c9f1fd3 |
children |
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/* * Copyright (C) Igor Sysoev */ #include <ngx_config.h> #include <ngx_core.h> #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER )) static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf); #if ( __i386__ ) static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf) { /* * we could not use %ebx as output parameter if gcc builds PIC, * and we could not save %ebx on stack, because %esp is used, * when the -fomit-frame-pointer optimization is specified. */ __asm__ ( " mov %%ebx, %%esi; " " cpuid; " " mov %%eax, (%1); " " mov %%ebx, 4(%1); " " mov %%edx, 8(%1); " " mov %%ecx, 12(%1); " " mov %%esi, %%ebx; " : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" ); } #else /* __amd64__ */ static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf) { uint32_t eax, ebx, ecx, edx; __asm__ ( "cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) ); buf[0] = eax; buf[1] = ebx; buf[2] = edx; buf[3] = ecx; } #endif /* auto detect the L2 cache line size of modern and widespread CPUs */ void ngx_cpuinfo(void) { u_char *vendor; uint32_t vbuf[5], cpu[4]; vbuf[0] = 0; vbuf[1] = 0; vbuf[2] = 0; vbuf[3] = 0; vbuf[4] = 0; ngx_cpuid(0, vbuf); vendor = (u_char *) &vbuf[1]; if (vbuf[0] == 0) { return; } ngx_cpuid(1, cpu); if (ngx_strcmp(vendor, "GenuineIntel") == 0) { switch (cpu[0] & 0xf00) { /* Pentium */ case 5: /* Pentium Pro, II, III */ case 6: ngx_cacheline_size = 32; break; /* * Pentium 4, although its cache line size is 64 bytes, * it prefetches up to two cache lines during memory read */ case 15: ngx_cacheline_size = 128; break; } } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) { ngx_cacheline_size = 64; } } #else void ngx_cpuinfo(void) { } #endif