Mercurial > hg > nginx
annotate src/os/unix/ngx_gcc_atomic_ppc.h @ 3440:88741ec7731a stable-0.7
merge r3294, r3305:
Fix a bug introduced in r2032: After a child process has read a terminate
message from a channel, the process tries to read the channel again.
The kernel (at least FreeBSD) may preempt the process and sends a SIGIO
signal to a master process. The master process sends a new terminate message,
the kernel switches again to the the child process, and the child process
reads the messages instead of an EAGAIN error. And this may repeat over
and over. Being that the child process can not exit the cycle and test
the termination flag set by the message handler.
The fix disallow the master process to send a new terminate message on
SIGIO signal reception. It may send the message only on SIGALARM signal.
| author | Igor Sysoev <igor@sysoev.ru> |
|---|---|
| date | Mon, 01 Feb 2010 15:49:36 +0000 |
| parents | c4f120548171 |
| children | d620f497c50f |
| rev | line source |
|---|---|
| 561 | 1 |
| 2 /* | |
| 3 * Copyright (C) Igor Sysoev | |
| 4 */ | |
| 5 | |
| 6 | |
| 7 /* | |
| 8 * The ppc assembler treats ";" as comment, so we have to use "\n". | |
| 9 * The minus in "bne-" is a hint for the branch prediction unit that | |
| 10 * this branch is unlikely to be taken. | |
| 11 * The "1b" means the nearest backward label "1" and the "1f" means | |
| 12 * the nearest forward label "1". | |
| 577 | 13 * |
| 561 | 14 * The "b" means that the base registers can be used only, i.e. |
| 15 * any register except r0. The r0 register always has a zero value and | |
| 16 * could not be used in "addi r0, r0, 1". | |
| 17 * The "=&b" means that no input registers can be used. | |
| 938 | 18 * |
| 19 * "sync" read and write barriers | |
| 20 * "isync" read barrier, is faster than "sync" | |
| 21 * "eieio" write barrier, is faster than "sync" | |
| 22 * "lwsync" write barrier, is faster than "eieio" on ppc64 | |
| 561 | 23 */ |
| 24 | |
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25 #if (NGX_PTR_SIZE == 8) |
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26 |
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27 static ngx_inline ngx_atomic_uint_t |
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28 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, |
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29 ngx_atomic_uint_t set) |
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30 { |
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31 ngx_atomic_uint_t res, temp; |
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32 |
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33 __asm__ volatile ( |
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34 |
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35 " li %0, 0 \n" /* preset "0" to "res" */ |
| 938 | 36 " lwsync \n" /* write barrier */ |
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37 "1: \n" |
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38 " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
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39 /* and store reservation */ |
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40 " cmpd %1, %3 \n" /* compare "temp" and "old" */ |
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41 " bne- 2f \n" /* not equal */ |
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42 " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
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43 /* is not cleared */ |
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44 " bne- 1b \n" /* the reservation was cleared */ |
| 938 | 45 " isync \n" /* read barrier */ |
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46 " li %0, 1 \n" /* set "1" to "res" */ |
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47 "2: \n" |
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48 |
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49 : "=&b" (res), "=&b" (temp) |
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50 : "b" (lock), "b" (old), "b" (set) |
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51 : "cc", "memory"); |
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52 |
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53 return res; |
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54 } |
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55 |
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56 |
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57 static ngx_inline ngx_atomic_int_t |
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58 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) |
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59 { |
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60 ngx_atomic_uint_t res, temp; |
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61 |
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62 __asm__ volatile ( |
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63 |
| 938 | 64 " lwsync \n" /* write barrier */ |
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65 "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ |
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66 /* and store reservation */ |
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67 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ |
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68 " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ |
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69 /* is not cleared */ |
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70 " bne- 1b \n" /* try again if reservation was cleared */ |
| 938 | 71 " isync \n" /* read barrier */ |
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72 |
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73 : "=&b" (res), "=&b" (temp) |
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74 : "b" (value), "b" (add) |
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75 : "cc", "memory"); |
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76 |
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77 return res; |
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78 } |
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79 |
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80 |
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81 #if (NGX_SMP) |
| 938 | 82 #define ngx_memory_barrier() \ |
| 83 __asm__ volatile ("isync \n lwsync \n" ::: "memory") | |
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84 #else |
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85 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") |
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86 #endif |
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87 |
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88 #else |
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89 |
| 561 | 90 static ngx_inline ngx_atomic_uint_t |
| 91 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, | |
| 92 ngx_atomic_uint_t set) | |
| 93 { | |
| 94 ngx_atomic_uint_t res, temp; | |
| 95 | |
| 96 __asm__ volatile ( | |
| 97 | |
| 98 " li %0, 0 \n" /* preset "0" to "res" */ | |
| 938 | 99 " eieio \n" /* write barrier */ |
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100 "1: \n" |
| 561 | 101 " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
| 102 /* and store reservation */ | |
| 103 " cmpw %1, %3 \n" /* compare "temp" and "old" */ | |
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104 " bne- 2f \n" /* not equal */ |
| 561 | 105 " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
| 106 /* is not cleared */ | |
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107 " bne- 1b \n" /* the reservation was cleared */ |
| 938 | 108 " isync \n" /* read barrier */ |
| 561 | 109 " li %0, 1 \n" /* set "1" to "res" */ |
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110 "2: \n" |
| 561 | 111 |
| 112 : "=&b" (res), "=&b" (temp) | |
| 113 : "b" (lock), "b" (old), "b" (set) | |
| 114 : "cc", "memory"); | |
| 115 | |
| 116 return res; | |
| 117 } | |
| 118 | |
| 119 | |
| 120 static ngx_inline ngx_atomic_int_t | |
| 121 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) | |
| 122 { | |
| 123 ngx_atomic_uint_t res, temp; | |
| 124 | |
| 125 __asm__ volatile ( | |
| 126 | |
| 938 | 127 " eieio \n" /* write barrier */ |
| 561 | 128 "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ |
| 129 /* and store reservation */ | |
| 130 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ | |
| 131 " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ | |
| 132 /* is not cleared */ | |
| 133 " bne- 1b \n" /* try again if reservation was cleared */ | |
| 938 | 134 " isync \n" /* read barrier */ |
| 561 | 135 |
| 136 : "=&b" (res), "=&b" (temp) | |
| 137 : "b" (value), "b" (add) | |
| 138 : "cc", "memory"); | |
| 139 | |
| 140 return res; | |
| 141 } | |
| 563 | 142 |
| 143 | |
| 144 #if (NGX_SMP) | |
| 938 | 145 #define ngx_memory_barrier() \ |
| 146 __asm__ volatile ("isync \n eieio \n" ::: "memory") | |
| 563 | 147 #else |
| 148 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") | |
| 149 #endif | |
| 611 | 150 |
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151 #endif |
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152 |
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153 |
| 611 | 154 #define ngx_cpu_pause() |