Mercurial > hg > nginx
annotate src/core/ngx_cpuinfo.c @ 9230:e14debe728b0 radix_with_skip
Closed the radix_with_skip branch.
The radix_with_skip branch is an archive of an experiment did in 2008,
and it is no longer relevant. It is now closed to avoid cluttering of
the branches list. If needed, closed branches still can be seen with
"hg branches --closed".
author | Maxim Dounin <mdounin@mdounin.ru> |
---|---|
date | Sat, 23 Mar 2024 04:30:45 +0300 |
parents | 8e88522cb6da |
children | b863be280d3b |
rev | line source |
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611 | 1 |
2 /* | |
3 * Copyright (C) Igor Sysoev | |
4 */ | |
5 | |
6 | |
7 #include <ngx_config.h> | |
8 #include <ngx_core.h> | |
9 | |
10 | |
11 #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER )) | |
12 | |
13 | |
14 static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf); | |
15 | |
16 | |
617 | 17 #if ( __i386__ ) |
18 | |
19 static ngx_inline void | |
20 ngx_cpuid(uint32_t i, uint32_t *buf) | |
21 { | |
22 | |
23 /* | |
24 * we could not use %ebx as output parameter if gcc builds PIC, | |
25 * and we could not save %ebx on stack, because %esp is used, | |
26 * when the -fomit-frame-pointer optimization is specified. | |
27 */ | |
28 | |
29 __asm__ ( | |
30 | |
31 " mov %%ebx, %%esi; " | |
32 | |
33 " cpuid; " | |
651 | 34 " mov %%eax, (%1); " |
35 " mov %%ebx, 4(%1); " | |
36 " mov %%edx, 8(%1); " | |
37 " mov %%ecx, 12(%1); " | |
617 | 38 |
39 " mov %%esi, %%ebx; " | |
40 | |
651 | 41 : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" ); |
617 | 42 } |
43 | |
44 | |
45 #else /* __amd64__ */ | |
46 | |
47 | |
611 | 48 static ngx_inline void |
49 ngx_cpuid(uint32_t i, uint32_t *buf) | |
50 { | |
51 uint32_t eax, ebx, ecx, edx; | |
52 | |
53 __asm__ ( | |
54 | |
55 "cpuid" | |
56 | |
57 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) ); | |
58 | |
59 buf[0] = eax; | |
60 buf[1] = ebx; | |
61 buf[2] = edx; | |
62 buf[3] = ecx; | |
63 } | |
64 | |
65 | |
617 | 66 #endif |
67 | |
68 | |
611 | 69 /* auto detect the L2 cache line size of modern and widespread CPUs */ |
70 | |
71 void | |
72 ngx_cpuinfo(void) | |
73 { | |
74 u_char *vendor; | |
75 uint32_t vbuf[5], cpu[4]; | |
76 | |
77 vbuf[0] = 0; | |
78 vbuf[1] = 0; | |
79 vbuf[2] = 0; | |
80 vbuf[3] = 0; | |
81 vbuf[4] = 0; | |
82 | |
83 ngx_cpuid(0, vbuf); | |
84 | |
85 vendor = (u_char *) &vbuf[1]; | |
86 | |
87 if (vbuf[0] == 0) { | |
88 return; | |
89 } | |
90 | |
91 ngx_cpuid(1, cpu); | |
92 | |
93 if (ngx_strcmp(vendor, "GenuineIntel") == 0) { | |
94 | |
1871
9afb84c7cc61
fix cache line size for Pentium 4
Igor Sysoev <igor@sysoev.ru>
parents:
651
diff
changeset
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95 switch ((cpu[0] & 0xf00) >> 8) { |
611 | 96 |
97 /* Pentium */ | |
98 case 5: | |
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parents:
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99 ngx_cacheline_size = 32; |
8e88522cb6da
detect L2 cache line size for Intel Core
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parents:
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100 break; |
8e88522cb6da
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parents:
1871
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101 |
611 | 102 /* Pentium Pro, II, III */ |
103 case 6: | |
104 ngx_cacheline_size = 32; | |
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parents:
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105 |
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parents:
1871
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106 if ((cpu[0] & 0xf0) >= 0xd0) { |
8e88522cb6da
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parents:
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107 /* Intel Core */ |
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parents:
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108 ngx_cacheline_size = 64; |
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
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109 } |
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
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110 |
611 | 111 break; |
112 | |
113 /* | |
114 * Pentium 4, although its cache line size is 64 bytes, | |
115 * it prefetches up to two cache lines during memory read | |
116 */ | |
117 case 15: | |
118 ngx_cacheline_size = 128; | |
119 break; | |
120 } | |
121 | |
122 } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) { | |
123 ngx_cacheline_size = 64; | |
124 } | |
125 } | |
126 | |
127 #else | |
128 | |
129 | |
130 void | |
131 ngx_cpuinfo(void) | |
132 { | |
133 } | |
134 | |
135 | |
136 #endif |