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comparison src/os/unix/ngx_gcc_atomic_amd64.h @ 1009:ee5f21acea76

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optimization
author Igor Sysoev <igor@sysoev.ru>
date Thu, 11 Jan 2007 16:07:38 +0000
parents f1ebccfd95f9
children d620f497c50f
comparison
equal deleted inserted replaced
1008:51d0884364fe 1009:ee5f21acea76
22 * rax = [m]; 22 * rax = [m];
23 * } 23 * }
24 * 24 *
25 * 25 *
26 * The "r" is any register, %rax (%r0) - %r16. 26 * The "r" is any register, %rax (%r0) - %r16.
27 * The "=a" and "a" are the %rax register. Although we can return result 27 * The "=a" and "a" are the %rax register.
28 * in any register, we use %rax because it is used in cmpxchgq anyway. 28 * Although we can return result in any register, we use "a" because it is
29 * used in cmpxchgq anyway. The result is actually in %al but not in $rax,
30 * however as the code is inlined gcc can test %al as well as %rax.
31 *
29 * The "cc" means that flags were changed. 32 * The "cc" means that flags were changed.
30 */ 33 */
31 34
32 static ngx_inline ngx_atomic_uint_t 35 static ngx_inline ngx_atomic_uint_t
33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, 36 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
34 ngx_atomic_uint_t set) 37 ngx_atomic_uint_t set)
35 { 38 {
36 ngx_atomic_uint_t res; 39 u_char res;
37 40
38 __asm__ volatile ( 41 __asm__ volatile (
39 42
40 NGX_SMP_LOCK 43 NGX_SMP_LOCK
41 " cmpxchgq %3, %1; " 44 " cmpxchgq %3, %1; "
42 " setz %b0; " 45 " sete %0; "
43 " movzbq %b0, %0; "
44 46
45 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory"); 47 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
46 48
47 return res; 49 return res;
48 } 50 }