Mercurial > hg > nginx-quic
view src/os/unix/ngx_gcc_atomic_ppc.h @ 4667:d05ab8793a69 stable-1.2
Merge of r4622, r4623: balancing changes.
*) Upstream: smooth weighted round-robin balancing.
For edge case weights like { 5, 1, 1 } we now produce { a, a, b, a, c, a, a }
sequence instead of { c, b, a, a, a, a, a } produced previously.
Algorithm is as follows: on each peer selection we increase current_weight
of each eligible peer by its weight, select peer with greatest current_weight
and reduce its current_weight by total number of weight points distributed
among peers.
In case of { 5, 1, 1 } weights this gives the following sequence of
current_weight's:
a b c
0 0 0 (initial state)
5 1 1 (a selected)
-2 1 1
3 2 2 (a selected)
-4 2 2
1 3 3 (b selected)
1 -4 3
6 -3 4 (a selected)
-1 -3 4
4 -2 5 (c selected)
4 -2 -2
9 -1 -1 (a selected)
2 -1 -1
7 0 0 (a selected)
0 0 0
To preserve weight reduction in case of failures the effective_weight
variable was introduced, which usually matches peer's weight, but is
reduced temporarily on peer failures.
This change also fixes loop with backup servers and proxy_next_upstream
http_404 (ticket #47), and skipping alive upstreams in some cases if there
are multiple dead ones (ticket #64).
*) Upstream: fixed ip_hash rebalancing with the "down" flag.
Due to weight being set to 0 for down peers, order of peers after sorting
wasn't the same as without the "down" flag (with down peers at the end),
resulting in client rebalancing for clients on other servers. The only
rebalancing which should happen after adding "down" to a server is one
for clients on the server.
The problem was introduced in r1377 (which fixed endless loop by setting
weight to 0 for down servers). The loop is no longer possible with new
smooth algorithm, so preserving original weight is safe.
| author | Maxim Dounin <mdounin@mdounin.ru> |
|---|---|
| date | Mon, 04 Jun 2012 11:21:58 +0000 |
| parents | d620f497c50f |
| children |
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/* * Copyright (C) Igor Sysoev * Copyright (C) Nginx, Inc. */ /* * The ppc assembler treats ";" as comment, so we have to use "\n". * The minus in "bne-" is a hint for the branch prediction unit that * this branch is unlikely to be taken. * The "1b" means the nearest backward label "1" and the "1f" means * the nearest forward label "1". * * The "b" means that the base registers can be used only, i.e. * any register except r0. The r0 register always has a zero value and * could not be used in "addi r0, r0, 1". * The "=&b" means that no input registers can be used. * * "sync" read and write barriers * "isync" read barrier, is faster than "sync" * "eieio" write barrier, is faster than "sync" * "lwsync" write barrier, is faster than "eieio" on ppc64 */ #if (NGX_PTR_SIZE == 8) static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " li %0, 0 \n" /* preset "0" to "res" */ " lwsync \n" /* write barrier */ "1: \n" " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ /* and store reservation */ " cmpd %1, %3 \n" /* compare "temp" and "old" */ " bne- 2f \n" /* not equal */ " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ /* is not cleared */ " bne- 1b \n" /* the reservation was cleared */ " isync \n" /* read barrier */ " li %0, 1 \n" /* set "1" to "res" */ "2: \n" : "=&b" (res), "=&b" (temp) : "b" (lock), "b" (old), "b" (set) : "cc", "memory"); return res; } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " lwsync \n" /* write barrier */ "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ /* and store reservation */ " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ /* is not cleared */ " bne- 1b \n" /* try again if reservation was cleared */ " isync \n" /* read barrier */ : "=&b" (res), "=&b" (temp) : "b" (value), "b" (add) : "cc", "memory"); return res; } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ("isync \n lwsync \n" ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #else static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " li %0, 0 \n" /* preset "0" to "res" */ " eieio \n" /* write barrier */ "1: \n" " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ /* and store reservation */ " cmpw %1, %3 \n" /* compare "temp" and "old" */ " bne- 2f \n" /* not equal */ " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ /* is not cleared */ " bne- 1b \n" /* the reservation was cleared */ " isync \n" /* read barrier */ " li %0, 1 \n" /* set "1" to "res" */ "2: \n" : "=&b" (res), "=&b" (temp) : "b" (lock), "b" (old), "b" (set) : "cc", "memory"); return res; } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t res, temp; __asm__ volatile ( " eieio \n" /* write barrier */ "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ /* and store reservation */ " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ /* is not cleared */ " bne- 1b \n" /* try again if reservation was cleared */ " isync \n" /* read barrier */ : "=&b" (res), "=&b" (temp) : "b" (value), "b" (add) : "cc", "memory"); return res; } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ("isync \n eieio \n" ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #endif #define ngx_cpu_pause()