Mercurial > hg > nginx-vendor-0-7
view src/os/unix/ngx_gcc_atomic_x86.h @ 496:116d5de7cbb6 NGINX_0_7_60
nginx 0.7.60
*) Feature: the "updating" parameter in "proxy_cache_use_stale" and
"fastcgi_cache_use_stale" directives.
*) Feature: the "keepalive_requests" directive.
*) Bugfix: in open_file_cache and proxy/fastcgi cache interaction on
start up.
*) Bugfix: open_file_cache might cache open file descriptors too long.
*) Bugfix: the "If-Modified-Since", "If-Range", etc. client request
header lines were passed to backend while caching if no
"proxy_set_header" directive was used with any parameters.
*) Bugfix: the "Set-Cookie" and "P3P" response header lines were not
hidden while caching if no "proxy_hide_header/fastcgi_hide_header"
directives were used with any parameters.
*) Bugfix: the ngx_http_image_filter_module did not support GIF87a
format.
Thanks to Denis Ilyinyh.
*) Bugfix: nginx could not be built modules on Solaris 10 and early;
the bug had appeared in 0.7.56.
*) Bugfix: XLST filter did not work in subrequests.
*) Bugfix: in relative paths handling in nginx/Windows.
*) Bugfix: in proxy_store, fastcgi_store, proxy_cache, and
fastcgi_cache in nginx/Windows.
author | Igor Sysoev <http://sysoev.ru> |
---|---|
date | Mon, 15 Jun 2009 00:00:00 +0400 |
parents | 052a7b1d40e5 |
children |
line wrap: on
line source
/* * Copyright (C) Igor Sysoev */ #if (NGX_SMP) #define NGX_SMP_LOCK "lock;" #else #define NGX_SMP_LOCK #endif /* * "cmpxchgl r, [m]": * * if (eax == [m]) { * zf = 1; * [m] = r; * } else { * zf = 0; * eax = [m]; * } * * * The "r" means the general register. * The "=a" and "a" are the %eax register. * Although we can return result in any register, we use "a" because it is * used in cmpxchgl anyway. The result is actually in %al but not in %eax, * however, as the code is inlined gcc can test %al as well as %eax, * and icc adds "movzbl %al, %eax" by itself. * * The "cc" means that flags were changed. */ static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { u_char res; __asm__ volatile ( NGX_SMP_LOCK " cmpxchgl %3, %1; " " sete %0; " : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory"); return res; } /* * "xaddl r, [m]": * * temp = [m]; * [m] += r; * r = temp; * * * The "+r" means the general register. * The "cc" means that flags were changed. */ #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 )) /* * icc 8.1 and 9.0 compile broken code with -march=pentium4 option: * ngx_atomic_fetch_add() always return the input "add" value, * so we use the gcc 2.7 version. * * icc 8.1 and 9.0 with -march=pentiumpro option or icc 7.1 compile * correct code. */ static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { __asm__ volatile ( NGX_SMP_LOCK " xaddl %0, %1; " : "+r" (add) : "m" (*value) : "cc", "memory"); return add; } #else /* * gcc 2.7 does not support "+r", so we have to use the fixed * %eax ("=a" and "a") and this adds two superfluous instructions in the end * of code, something like this: "mov %eax, %edx / mov %edx, %eax". */ static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t old; __asm__ volatile ( NGX_SMP_LOCK " xaddl %2, %1; " : "=a" (old) : "m" (*value), "a" (add) : "cc", "memory"); return old; } #endif /* * on x86 the write operations go in a program order, so we need only * to disable the gcc reorder optimizations */ #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") /* old as does not support "pause" opcode */ #define ngx_cpu_pause() __asm__ (".byte 0xf3, 0x90")