Mercurial > hg > nginx-vendor-1-0
view src/os/unix/ngx_gcc_atomic_sparc64.h @ 270:6eb1e38f0f1f NGINX_0_5_5
nginx 0.5.5
*) Change: the -v switch does not show compiler information any more.
*) Feature: the -V switch.
*) Feature: the "worker_rlimit_core" directive supports size in K, M,
and G.
*) Bugfix: the nginx.pm module now could be installed by an
unprivileged user.
*) Bugfix: a segmentation fault might occur if the $r->request_body or
$r->request_body_file methods were used.
*) Bugfix: the ppc platform specific bugs.
author | Igor Sysoev <http://sysoev.ru> |
---|---|
date | Sun, 24 Dec 2006 00:00:00 +0300 |
parents | 73e8476f9142 |
children | ad25218fd14b |
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/* * Copyright (C) Igor Sysoev */ /* * "casa [r1] 0x80, r2, r0" and * "casxa [r1] 0x80, r2, r0" do the following: * * if ([r1] == r2) { * swap(r0, [r1]); * } else { * r0 = [r1]; * } * * so "r0 == r2" means that the operation was successfull. * * * The "r" means the general register. * The "+r" means the general register used for both input and output. */ #if (NGX_PTR_SIZE == 4) #define NGX_CASA "casa" #else #define NGX_CASA "casxa" #endif static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { __asm__ volatile ( NGX_CASA " [%1] 0x80, %2, %0" : "+r" (set) : "r" (lock), "r" (old) : "memory"); return (set == old); } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t old, res; old = *value; for ( ;; ) { res = old + add; __asm__ volatile ( NGX_CASA " [%1] 0x80, %2, %0" : "+r" (res) : "r" (value), "r" (old) : "memory"); if (res == old) { return res; } old = res; } } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ( \ "membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" \ ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #define ngx_cpu_pause()