Mercurial > hg > nginx-vendor-current
view src/os/unix/ngx_gcc_atomic_sparc64.h @ 588:b6a5942a4e6a NGINX_0_8_46
nginx 0.8.46
*) Change: now the "proxy_no_cache", "fastcgi_no_cache",
"uwsgi_no_cache", and "scgi_no_cache" directives affect on a cached
response saving only.
*) Feature: the "proxy_cache_bypass", "fastcgi_cache_bypass",
"uwsgi_cache_bypass", and "scgi_cache_bypass" directives.
*) Bugfix: nginx did not free memory in cache keys zones if there was
an error during working with backend: the memory was freed only
after inactivity time or on memory low condition.
author | Igor Sysoev <http://sysoev.ru> |
---|---|
date | Mon, 19 Jul 2010 00:00:00 +0400 |
parents | 73e8476f9142 |
children | d0f7a625f27c |
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/* * Copyright (C) Igor Sysoev */ /* * "casa [r1] 0x80, r2, r0" and * "casxa [r1] 0x80, r2, r0" do the following: * * if ([r1] == r2) { * swap(r0, [r1]); * } else { * r0 = [r1]; * } * * so "r0 == r2" means that the operation was successfull. * * * The "r" means the general register. * The "+r" means the general register used for both input and output. */ #if (NGX_PTR_SIZE == 4) #define NGX_CASA "casa" #else #define NGX_CASA "casxa" #endif static ngx_inline ngx_atomic_uint_t ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, ngx_atomic_uint_t set) { __asm__ volatile ( NGX_CASA " [%1] 0x80, %2, %0" : "+r" (set) : "r" (lock), "r" (old) : "memory"); return (set == old); } static ngx_inline ngx_atomic_int_t ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) { ngx_atomic_uint_t old, res; old = *value; for ( ;; ) { res = old + add; __asm__ volatile ( NGX_CASA " [%1] 0x80, %2, %0" : "+r" (res) : "r" (value), "r" (old) : "memory"); if (res == old) { return res; } old = res; } } #if (NGX_SMP) #define ngx_memory_barrier() \ __asm__ volatile ( \ "membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" \ ::: "memory") #else #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") #endif #define ngx_cpu_pause()