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561
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1
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2 /*
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3 * Copyright (C) Igor Sysoev
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4412
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4 * Copyright (C) Nginx, Inc.
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561
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5 */
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6
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7
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8 #if (NGX_SMP)
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9 #define NGX_SMP_LOCK "lock;"
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10 #else
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11 #define NGX_SMP_LOCK
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12 #endif
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13
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14
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15 /*
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16 * "cmpxchgq r, [m]":
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17 *
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18 * if (rax == [m]) {
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19 * zf = 1;
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20 * [m] = r;
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21 * } else {
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22 * zf = 0;
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23 * rax = [m];
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24 * }
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25 *
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26 *
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27 * The "r" is any register, %rax (%r0) - %r16.
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1009
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28 * The "=a" and "a" are the %rax register.
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29 * Although we can return result in any register, we use "a" because it is
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30 * used in cmpxchgq anyway. The result is actually in %al but not in $rax,
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31 * however as the code is inlined gcc can test %al as well as %rax.
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32 *
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33 * The "cc" means that flags were changed.
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34 */
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35
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36 static ngx_inline ngx_atomic_uint_t
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37 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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38 ngx_atomic_uint_t set)
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577
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39 {
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1009
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40 u_char res;
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41
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42 __asm__ volatile (
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43
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44 NGX_SMP_LOCK
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45 " cmpxchgq %3, %1; "
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1009
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46 " sete %0; "
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47
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48 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
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49
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50 return res;
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51 }
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52
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53
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54 /*
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55 * "xaddq r, [m]":
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56 *
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57 * temp = [m];
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58 * [m] += r;
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59 * r = temp;
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60 *
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61 *
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62 * The "+r" is any register, %rax (%r0) - %r16.
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63 * The "cc" means that flags were changed.
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64 */
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65
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66 static ngx_inline ngx_atomic_int_t
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67 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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68 {
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69 __asm__ volatile (
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70
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71 NGX_SMP_LOCK
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72 " xaddq %0, %1; "
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73
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74 : "+r" (add) : "m" (*value) : "cc", "memory");
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75
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76 return add;
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77 }
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78
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79
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611
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80 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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81
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82 #define ngx_cpu_pause() __asm__ ("pause")
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