Mercurial > hg > nginx
annotate src/core/ngx_cpuinfo.c @ 3992:a1dd9dc754ab
A new fix for the case when ssl_session_cache defined, but ssl is not
enabled in any server. The previous r1033 does not help when unused zone
becomes used after reconfiguration, so it is backed out.
The initial thought was to make SSL modules independed from SSL implementation
and to keep OpenSSL code dependance as much as in separate files.
| author | Igor Sysoev <igor@sysoev.ru> |
|---|---|
| date | Thu, 04 Aug 2011 11:12:30 +0000 |
| parents | b863be280d3b |
| children | d620f497c50f |
| rev | line source |
|---|---|
| 611 | 1 |
| 2 /* | |
| 3 * Copyright (C) Igor Sysoev | |
| 4 */ | |
| 5 | |
| 6 | |
| 7 #include <ngx_config.h> | |
| 8 #include <ngx_core.h> | |
| 9 | |
| 10 | |
| 11 #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER )) | |
| 12 | |
| 13 | |
| 14 static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf); | |
| 15 | |
| 16 | |
| 617 | 17 #if ( __i386__ ) |
| 18 | |
| 19 static ngx_inline void | |
| 20 ngx_cpuid(uint32_t i, uint32_t *buf) | |
| 21 { | |
| 22 | |
| 23 /* | |
| 24 * we could not use %ebx as output parameter if gcc builds PIC, | |
| 25 * and we could not save %ebx on stack, because %esp is used, | |
| 26 * when the -fomit-frame-pointer optimization is specified. | |
| 27 */ | |
| 28 | |
| 29 __asm__ ( | |
| 30 | |
| 31 " mov %%ebx, %%esi; " | |
| 32 | |
| 33 " cpuid; " | |
| 651 | 34 " mov %%eax, (%1); " |
| 35 " mov %%ebx, 4(%1); " | |
| 36 " mov %%edx, 8(%1); " | |
| 37 " mov %%ecx, 12(%1); " | |
| 617 | 38 |
| 39 " mov %%esi, %%ebx; " | |
| 40 | |
| 651 | 41 : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" ); |
| 617 | 42 } |
| 43 | |
| 44 | |
| 45 #else /* __amd64__ */ | |
| 46 | |
| 47 | |
| 611 | 48 static ngx_inline void |
| 49 ngx_cpuid(uint32_t i, uint32_t *buf) | |
| 50 { | |
| 51 uint32_t eax, ebx, ecx, edx; | |
| 52 | |
| 53 __asm__ ( | |
| 54 | |
| 55 "cpuid" | |
| 56 | |
| 57 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) ); | |
| 58 | |
| 59 buf[0] = eax; | |
| 60 buf[1] = ebx; | |
| 61 buf[2] = edx; | |
| 62 buf[3] = ecx; | |
| 63 } | |
| 64 | |
| 65 | |
| 617 | 66 #endif |
| 67 | |
| 68 | |
| 611 | 69 /* auto detect the L2 cache line size of modern and widespread CPUs */ |
| 70 | |
| 71 void | |
| 72 ngx_cpuinfo(void) | |
| 73 { | |
| 74 u_char *vendor; | |
|
2613
b863be280d3b
update cpuid for Core 2 and Atom
Igor Sysoev <igor@sysoev.ru>
parents:
1872
diff
changeset
|
75 uint32_t vbuf[5], cpu[4], model; |
| 611 | 76 |
| 77 vbuf[0] = 0; | |
| 78 vbuf[1] = 0; | |
| 79 vbuf[2] = 0; | |
| 80 vbuf[3] = 0; | |
| 81 vbuf[4] = 0; | |
| 82 | |
| 83 ngx_cpuid(0, vbuf); | |
| 84 | |
| 85 vendor = (u_char *) &vbuf[1]; | |
| 86 | |
| 87 if (vbuf[0] == 0) { | |
| 88 return; | |
| 89 } | |
| 90 | |
| 91 ngx_cpuid(1, cpu); | |
| 92 | |
| 93 if (ngx_strcmp(vendor, "GenuineIntel") == 0) { | |
| 94 | |
|
1871
9afb84c7cc61
fix cache line size for Pentium 4
Igor Sysoev <igor@sysoev.ru>
parents:
651
diff
changeset
|
95 switch ((cpu[0] & 0xf00) >> 8) { |
| 611 | 96 |
| 97 /* Pentium */ | |
| 98 case 5: | |
|
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detect L2 cache line size for Intel Core
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parents:
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diff
changeset
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99 ngx_cacheline_size = 32; |
|
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detect L2 cache line size for Intel Core
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parents:
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diff
changeset
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100 break; |
|
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Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
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101 |
| 611 | 102 /* Pentium Pro, II, III */ |
| 103 case 6: | |
| 104 ngx_cacheline_size = 32; | |
|
1872
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
|
105 |
|
2613
b863be280d3b
update cpuid for Core 2 and Atom
Igor Sysoev <igor@sysoev.ru>
parents:
1872
diff
changeset
|
106 model = ((cpu[0] & 0xf0000) >> 8) | (cpu[0] & 0xf0); |
|
b863be280d3b
update cpuid for Core 2 and Atom
Igor Sysoev <igor@sysoev.ru>
parents:
1872
diff
changeset
|
107 |
|
b863be280d3b
update cpuid for Core 2 and Atom
Igor Sysoev <igor@sysoev.ru>
parents:
1872
diff
changeset
|
108 if (model >= 0xd0) { |
|
b863be280d3b
update cpuid for Core 2 and Atom
Igor Sysoev <igor@sysoev.ru>
parents:
1872
diff
changeset
|
109 /* Intel Core, Core 2, Atom */ |
|
1872
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
|
110 ngx_cacheline_size = 64; |
|
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
|
111 } |
|
8e88522cb6da
detect L2 cache line size for Intel Core
Igor Sysoev <igor@sysoev.ru>
parents:
1871
diff
changeset
|
112 |
| 611 | 113 break; |
| 114 | |
| 115 /* | |
| 116 * Pentium 4, although its cache line size is 64 bytes, | |
| 117 * it prefetches up to two cache lines during memory read | |
| 118 */ | |
| 119 case 15: | |
| 120 ngx_cacheline_size = 128; | |
| 121 break; | |
| 122 } | |
| 123 | |
| 124 } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) { | |
| 125 ngx_cacheline_size = 64; | |
| 126 } | |
| 127 } | |
| 128 | |
| 129 #else | |
| 130 | |
| 131 | |
| 132 void | |
| 133 ngx_cpuinfo(void) | |
| 134 { | |
| 135 } | |
| 136 | |
| 137 | |
| 138 #endif |