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561
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1
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2 /*
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3 * Copyright (C) Igor Sysoev
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4 */
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5
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6
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7 #if (NGX_SMP)
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8 #define NGX_SMP_LOCK "lock;"
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9 #else
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10 #define NGX_SMP_LOCK
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11 #endif
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12
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13
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14 /*
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15 * "cmpxchgq r, [m]":
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16 *
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17 * if (rax == [m]) {
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18 * zf = 1;
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19 * [m] = r;
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20 * } else {
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21 * zf = 0;
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22 * rax = [m];
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23 * }
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24 *
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25 *
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26 * The "r" is any register, %rax (%r0) - %r16.
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27 * The "=a" and "a" are the %rax register. Although we can return result
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28 * in any register, we use %rax because it is used in cmpxchgq anyway.
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29 * The "cc" means that flags were changed.
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30 */
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31
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32 static ngx_inline ngx_atomic_uint_t
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33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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34 ngx_atomic_uint_t set)
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577
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35 {
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561
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36 ngx_atomic_uint_t res;
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37
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38 __asm__ volatile (
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39
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40 NGX_SMP_LOCK
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41 " cmpxchgq %3, %1; "
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42 " setz %b0; "
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43 " movzbq %b0, %0; "
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44
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45 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
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46
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47 return res;
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48 }
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49
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50
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51 /*
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52 * "xaddq r, [m]":
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53 *
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54 * temp = [m];
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55 * [m] += r;
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56 * r = temp;
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57 *
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58 *
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59 * The "+r" is any register, %rax (%r0) - %r16.
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60 * The "cc" means that flags were changed.
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61 */
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62
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63 static ngx_inline ngx_atomic_int_t
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64 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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65 {
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66 __asm__ volatile (
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67
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68 NGX_SMP_LOCK
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69 " xaddq %0, %1; "
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70
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71 : "+q" (add) : "m" (*value) : "cc", "memory");
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72
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73 return add;
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74 }
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563
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75
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76
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611
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77 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
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78
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79 #define ngx_cpu_pause() __asm__ ("pause")
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