Mercurial > hg > nginx
comparison src/os/unix/ngx_gcc_atomic_ppc.h @ 938:c4f120548171
use the right memory barriers
author | Igor Sysoev <igor@sysoev.ru> |
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date | Thu, 21 Dec 2006 15:47:00 +0000 |
parents | fc1358d3d23a |
children | d620f497c50f |
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937:fc1358d3d23a | 938:c4f120548171 |
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13 * | 13 * |
14 * The "b" means that the base registers can be used only, i.e. | 14 * The "b" means that the base registers can be used only, i.e. |
15 * any register except r0. The r0 register always has a zero value and | 15 * any register except r0. The r0 register always has a zero value and |
16 * could not be used in "addi r0, r0, 1". | 16 * could not be used in "addi r0, r0, 1". |
17 * The "=&b" means that no input registers can be used. | 17 * The "=&b" means that no input registers can be used. |
18 * | |
19 * "sync" read and write barriers | |
20 * "isync" read barrier, is faster than "sync" | |
21 * "eieio" write barrier, is faster than "sync" | |
22 * "lwsync" write barrier, is faster than "eieio" on ppc64 | |
18 */ | 23 */ |
19 | 24 |
20 #if (NGX_PTR_SIZE == 8) | 25 #if (NGX_PTR_SIZE == 8) |
21 | 26 |
22 static ngx_inline ngx_atomic_uint_t | 27 static ngx_inline ngx_atomic_uint_t |
26 ngx_atomic_uint_t res, temp; | 31 ngx_atomic_uint_t res, temp; |
27 | 32 |
28 __asm__ volatile ( | 33 __asm__ volatile ( |
29 | 34 |
30 " li %0, 0 \n" /* preset "0" to "res" */ | 35 " li %0, 0 \n" /* preset "0" to "res" */ |
36 " lwsync \n" /* write barrier */ | |
31 "1: \n" | 37 "1: \n" |
32 " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ | 38 " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
33 /* and store reservation */ | 39 /* and store reservation */ |
34 " cmpd %1, %3 \n" /* compare "temp" and "old" */ | 40 " cmpd %1, %3 \n" /* compare "temp" and "old" */ |
35 " bne- 2f \n" /* not equal */ | 41 " bne- 2f \n" /* not equal */ |
36 " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ | 42 " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
37 /* is not cleared */ | 43 /* is not cleared */ |
38 " bne- 1b \n" /* the reservation was cleared */ | 44 " bne- 1b \n" /* the reservation was cleared */ |
45 " isync \n" /* read barrier */ | |
39 " li %0, 1 \n" /* set "1" to "res" */ | 46 " li %0, 1 \n" /* set "1" to "res" */ |
40 "2: \n" | 47 "2: \n" |
41 | 48 |
42 : "=&b" (res), "=&b" (temp) | 49 : "=&b" (res), "=&b" (temp) |
43 : "b" (lock), "b" (old), "b" (set) | 50 : "b" (lock), "b" (old), "b" (set) |
52 { | 59 { |
53 ngx_atomic_uint_t res, temp; | 60 ngx_atomic_uint_t res, temp; |
54 | 61 |
55 __asm__ volatile ( | 62 __asm__ volatile ( |
56 | 63 |
64 " lwsync \n" /* write barrier */ | |
57 "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ | 65 "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ |
58 /* and store reservation */ | 66 /* and store reservation */ |
59 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ | 67 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ |
60 " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ | 68 " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ |
61 /* is not cleared */ | 69 /* is not cleared */ |
62 " bne- 1b \n" /* try again if reservation was cleared */ | 70 " bne- 1b \n" /* try again if reservation was cleared */ |
71 " isync \n" /* read barrier */ | |
63 | 72 |
64 : "=&b" (res), "=&b" (temp) | 73 : "=&b" (res), "=&b" (temp) |
65 : "b" (value), "b" (add) | 74 : "b" (value), "b" (add) |
66 : "cc", "memory"); | 75 : "cc", "memory"); |
67 | 76 |
68 return res; | 77 return res; |
69 } | 78 } |
70 | 79 |
71 | 80 |
72 #if (NGX_SMP) | 81 #if (NGX_SMP) |
73 #define ngx_memory_barrier() __asm__ volatile ("lwsync\n" ::: "memory") | 82 #define ngx_memory_barrier() \ |
83 __asm__ volatile ("isync \n lwsync \n" ::: "memory") | |
74 #else | 84 #else |
75 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") | 85 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") |
76 #endif | 86 #endif |
77 | 87 |
78 #else | 88 #else |
84 ngx_atomic_uint_t res, temp; | 94 ngx_atomic_uint_t res, temp; |
85 | 95 |
86 __asm__ volatile ( | 96 __asm__ volatile ( |
87 | 97 |
88 " li %0, 0 \n" /* preset "0" to "res" */ | 98 " li %0, 0 \n" /* preset "0" to "res" */ |
99 " eieio \n" /* write barrier */ | |
89 "1: \n" | 100 "1: \n" |
90 " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ | 101 " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
91 /* and store reservation */ | 102 /* and store reservation */ |
92 " cmpw %1, %3 \n" /* compare "temp" and "old" */ | 103 " cmpw %1, %3 \n" /* compare "temp" and "old" */ |
93 " bne- 2f \n" /* not equal */ | 104 " bne- 2f \n" /* not equal */ |
94 " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ | 105 " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
95 /* is not cleared */ | 106 /* is not cleared */ |
96 " bne- 1b \n" /* the reservation was cleared */ | 107 " bne- 1b \n" /* the reservation was cleared */ |
108 " isync \n" /* read barrier */ | |
97 " li %0, 1 \n" /* set "1" to "res" */ | 109 " li %0, 1 \n" /* set "1" to "res" */ |
98 "2: \n" | 110 "2: \n" |
99 | 111 |
100 : "=&b" (res), "=&b" (temp) | 112 : "=&b" (res), "=&b" (temp) |
101 : "b" (lock), "b" (old), "b" (set) | 113 : "b" (lock), "b" (old), "b" (set) |
110 { | 122 { |
111 ngx_atomic_uint_t res, temp; | 123 ngx_atomic_uint_t res, temp; |
112 | 124 |
113 __asm__ volatile ( | 125 __asm__ volatile ( |
114 | 126 |
127 " eieio \n" /* write barrier */ | |
115 "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ | 128 "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ |
116 /* and store reservation */ | 129 /* and store reservation */ |
117 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ | 130 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ |
118 " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ | 131 " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ |
119 /* is not cleared */ | 132 /* is not cleared */ |
120 " bne- 1b \n" /* try again if reservation was cleared */ | 133 " bne- 1b \n" /* try again if reservation was cleared */ |
134 " isync \n" /* read barrier */ | |
121 | 135 |
122 : "=&b" (res), "=&b" (temp) | 136 : "=&b" (res), "=&b" (temp) |
123 : "b" (value), "b" (add) | 137 : "b" (value), "b" (add) |
124 : "cc", "memory"); | 138 : "cc", "memory"); |
125 | 139 |
126 return res; | 140 return res; |
127 } | 141 } |
128 | 142 |
129 | 143 |
130 #if (NGX_SMP) | 144 #if (NGX_SMP) |
131 #define ngx_memory_barrier() __asm__ volatile ("sync\n" ::: "memory") | 145 #define ngx_memory_barrier() \ |
146 __asm__ volatile ("isync \n eieio \n" ::: "memory") | |
132 #else | 147 #else |
133 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") | 148 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") |
134 #endif | 149 #endif |
135 | 150 |
136 #endif | 151 #endif |