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comparison src/os/unix/ngx_gcc_atomic_x86.h @ 274:052a7b1d40e5 NGINX_0_5_7

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nginx 0.5.7 *) Feature: the ssl_session_cache storage optimization. *) Bugfixes in the "ssl_session_cache" and "limit_zone" directives. *) Bugfix: the segmentation fault was occurred on start or while reconfiguration if the "ssl_session_cache" or "limit_zone" directives were used on 64-bit platforms. *) Bugfix: a segmentation fault occurred if the "add_before_body" or "add_after_body" directives were used and there was no "Content-Type" header line in response. *) Bugfix: the OpenSSL library was always built with the threads support. Thanks to Den Ivanov. *) Bugfix: the PCRE-6.5+ library and the icc compiler compatibility.
author Igor Sysoev <http://sysoev.ru>
date Mon, 15 Jan 2007 00:00:00 +0300
parents 73e8476f9142
children 5c576ea5dbd9
comparison
equal deleted inserted replaced
273:60df8db42ffb 274:052a7b1d40e5
21 * zf = 0; 21 * zf = 0;
22 * eax = [m]; 22 * eax = [m];
23 * } 23 * }
24 * 24 *
25 * 25 *
26 * The "q" is any of the %eax, %ebx, %ecx, or %edx registers. 26 * The "r" means the general register.
27 * The "=a" and "a" are the %eax register. Although we can return result 27 * The "=a" and "a" are the %eax register.
28 * in any register, we use %eax because it is used in cmpxchgl anyway. 28 * Although we can return result in any register, we use "a" because it is
29 * used in cmpxchgl anyway. The result is actually in %al but not in %eax,
30 * however, as the code is inlined gcc can test %al as well as %eax,
31 * and icc adds "movzbl %al, %eax" by itself.
32 *
29 * The "cc" means that flags were changed. 33 * The "cc" means that flags were changed.
30 */ 34 */
31 35
32 static ngx_inline ngx_atomic_uint_t 36 static ngx_inline ngx_atomic_uint_t
33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, 37 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
34 ngx_atomic_uint_t set) 38 ngx_atomic_uint_t set)
35 { 39 {
36 ngx_atomic_uint_t res; 40 u_char res;
37 41
38 __asm__ volatile ( 42 __asm__ volatile (
39 43
40 NGX_SMP_LOCK 44 NGX_SMP_LOCK
41 " cmpxchgl %3, %1; " 45 " cmpxchgl %3, %1; "
42 " setz %b0; " 46 " sete %0; "
43 " movzbl %b0, %0; "
44 47
45 : "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory"); 48 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
46 49
47 return res; 50 return res;
48 } 51 }
49 52
50 53
54 * temp = [m]; 57 * temp = [m];
55 * [m] += r; 58 * [m] += r;
56 * r = temp; 59 * r = temp;
57 * 60 *
58 * 61 *
59 * The "+q" is any of the %eax, %ebx, %ecx, or %edx registers. 62 * The "+r" means the general register.
60 * The "cc" means that flags were changed. 63 * The "cc" means that flags were changed.
61 */ 64 */
62 65
63 66
64 #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 )) 67 #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 ))
78 __asm__ volatile ( 81 __asm__ volatile (
79 82
80 NGX_SMP_LOCK 83 NGX_SMP_LOCK
81 " xaddl %0, %1; " 84 " xaddl %0, %1; "
82 85
83 : "+q" (add) : "m" (*value) : "cc", "memory"); 86 : "+r" (add) : "m" (*value) : "cc", "memory");
84 87
85 return add; 88 return add;
86 } 89 }
87 90
88 91
89 #else 92 #else
90 93
91 /* 94 /*
92 * gcc 2.7 does not support "+q", so we have to use the fixed %eax ("=a" and 95 * gcc 2.7 does not support "+r", so we have to use the fixed
93 * "a") and this adds two superfluous instructions in the end of code, 96 * %eax ("=a" and "a") and this adds two superfluous instructions in the end
94 * something like this: "mov %eax, %edx / mov %edx, %eax". 97 * of code, something like this: "mov %eax, %edx / mov %edx, %eax".
95 */ 98 */
96 99
97 static ngx_inline ngx_atomic_int_t 100 static ngx_inline ngx_atomic_int_t
98 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) 101 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
99 { 102 {