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diff src/os/unix/ngx_gcc_atomic_x86.h @ 274:052a7b1d40e5 NGINX_0_5_7

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nginx 0.5.7 *) Feature: the ssl_session_cache storage optimization. *) Bugfixes in the "ssl_session_cache" and "limit_zone" directives. *) Bugfix: the segmentation fault was occurred on start or while reconfiguration if the "ssl_session_cache" or "limit_zone" directives were used on 64-bit platforms. *) Bugfix: a segmentation fault occurred if the "add_before_body" or "add_after_body" directives were used and there was no "Content-Type" header line in response. *) Bugfix: the OpenSSL library was always built with the threads support. Thanks to Den Ivanov. *) Bugfix: the PCRE-6.5+ library and the icc compiler compatibility.
author Igor Sysoev <http://sysoev.ru>
date Mon, 15 Jan 2007 00:00:00 +0300
parents 73e8476f9142
children 5c576ea5dbd9
line wrap: on
line diff
--- a/src/os/unix/ngx_gcc_atomic_x86.h
+++ b/src/os/unix/ngx_gcc_atomic_x86.h
@@ -23,9 +23,13 @@
  *     }
  *
  *
- * The "q" is any of the %eax, %ebx, %ecx, or %edx registers.
- * The "=a" and "a" are the %eax register.  Although we can return result
- * in any register, we use %eax because it is used in cmpxchgl anyway.
+ * The "r" means the general register.
+ * The "=a" and "a" are the %eax register.
+ * Although we can return result in any register, we use "a" because it is
+ * used in cmpxchgl anyway.  The result is actually in %al but not in %eax,
+ * however, as the code is inlined gcc can test %al as well as %eax,
+ * and icc adds "movzbl %al, %eax" by itself.
+ *
  * The "cc" means that flags were changed.
  */
 
@@ -33,16 +37,15 @@ static ngx_inline ngx_atomic_uint_t
 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
     ngx_atomic_uint_t set)
 {
-    ngx_atomic_uint_t  res;
+    u_char  res;
 
     __asm__ volatile (
 
          NGX_SMP_LOCK
     "    cmpxchgl  %3, %1;   "
-    "    setz      %b0;      "
-    "    movzbl    %b0, %0;  "
+    "    sete      %0;       "
 
-    : "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory");
+    : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
 
     return res;
 }
@@ -56,7 +59,7 @@ ngx_atomic_cmp_set(ngx_atomic_t *lock, n
  *     r = temp;
  *
  *
- * The "+q" is any of the %eax, %ebx, %ecx, or %edx registers.
+ * The "+r" means the general register.
  * The "cc" means that flags were changed.
  */
 
@@ -80,7 +83,7 @@ ngx_atomic_fetch_add(ngx_atomic_t *value
          NGX_SMP_LOCK
     "    xaddl  %0, %1;   "
 
-    : "+q" (add) : "m" (*value) : "cc", "memory");
+    : "+r" (add) : "m" (*value) : "cc", "memory");
 
     return add;
 }
@@ -89,9 +92,9 @@ ngx_atomic_fetch_add(ngx_atomic_t *value
 #else
 
 /*
- * gcc 2.7 does not support "+q", so we have to use the fixed %eax ("=a" and
- * "a") and this adds two superfluous instructions in the end of code,
- * something like this: "mov %eax, %edx / mov %edx, %eax".
+ * gcc 2.7 does not support "+r", so we have to use the fixed
+ * %eax ("=a" and "a") and this adds two superfluous instructions in the end
+ * of code, something like this: "mov %eax, %edx / mov %edx, %eax".
  */
 
 static ngx_inline ngx_atomic_int_t