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160
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1
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2 /*
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3 * Copyright (C) Igor Sysoev
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660
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4 * Copyright (C) Nginx, Inc.
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160
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5 */
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6
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7
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8 #include <ngx_config.h>
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9 #include <ngx_core.h>
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10
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11
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12 #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER ))
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13
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14
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15 static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf);
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16
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17
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166
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18 #if ( __i386__ )
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19
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20 static ngx_inline void
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21 ngx_cpuid(uint32_t i, uint32_t *buf)
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22 {
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23
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24 /*
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25 * we could not use %ebx as output parameter if gcc builds PIC,
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26 * and we could not save %ebx on stack, because %esp is used,
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27 * when the -fomit-frame-pointer optimization is specified.
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28 */
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29
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30 __asm__ (
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31
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32 " mov %%ebx, %%esi; "
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33
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34 " cpuid; "
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200
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35 " mov %%eax, (%1); "
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36 " mov %%ebx, 4(%1); "
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37 " mov %%edx, 8(%1); "
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38 " mov %%ecx, 12(%1); "
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166
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39
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40 " mov %%esi, %%ebx; "
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41
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200
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42 : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" );
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166
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43 }
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44
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45
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46 #else /* __amd64__ */
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47
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48
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160
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49 static ngx_inline void
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50 ngx_cpuid(uint32_t i, uint32_t *buf)
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51 {
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52 uint32_t eax, ebx, ecx, edx;
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53
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54 __asm__ (
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55
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56 "cpuid"
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57
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58 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) );
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59
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60 buf[0] = eax;
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61 buf[1] = ebx;
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62 buf[2] = edx;
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63 buf[3] = ecx;
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64 }
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65
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66
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166
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67 #endif
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68
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69
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160
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70 /* auto detect the L2 cache line size of modern and widespread CPUs */
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71
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72 void
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73 ngx_cpuinfo(void)
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74 {
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75 u_char *vendor;
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468
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76 uint32_t vbuf[5], cpu[4], model;
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160
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77
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78 vbuf[0] = 0;
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79 vbuf[1] = 0;
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80 vbuf[2] = 0;
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81 vbuf[3] = 0;
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82 vbuf[4] = 0;
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83
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84 ngx_cpuid(0, vbuf);
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85
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86 vendor = (u_char *) &vbuf[1];
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87
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88 if (vbuf[0] == 0) {
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89 return;
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90 }
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91
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92 ngx_cpuid(1, cpu);
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93
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94 if (ngx_strcmp(vendor, "GenuineIntel") == 0) {
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95
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364
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96 switch ((cpu[0] & 0xf00) >> 8) {
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160
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97
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98 /* Pentium */
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99 case 5:
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364
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100 ngx_cacheline_size = 32;
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101 break;
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102
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160
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103 /* Pentium Pro, II, III */
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104 case 6:
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105 ngx_cacheline_size = 32;
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364
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106
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468
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107 model = ((cpu[0] & 0xf0000) >> 8) | (cpu[0] & 0xf0);
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108
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109 if (model >= 0xd0) {
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110 /* Intel Core, Core 2, Atom */
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364
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111 ngx_cacheline_size = 64;
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112 }
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113
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160
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114 break;
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115
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116 /*
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117 * Pentium 4, although its cache line size is 64 bytes,
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118 * it prefetches up to two cache lines during memory read
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119 */
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120 case 15:
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121 ngx_cacheline_size = 128;
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122 break;
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123 }
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124
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125 } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) {
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126 ngx_cacheline_size = 64;
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127 }
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128 }
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129
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130 #else
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131
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132
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133 void
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134 ngx_cpuinfo(void)
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135 {
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136 }
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137
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138
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139 #endif
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