Mercurial > hg > nginx
annotate src/os/unix/ngx_gcc_atomic_ppc.h @ 7142:b9d919b53593 stable-1.12
Stream: relaxed next upstream condition (ticket #1317).
When switching to a next upstream, some buffers could be stuck in the middle
of the filter chain. A condition existed that raised an error when this
happened. As it turned out, this condition prevented switching to a next
upstream if ssl preread was used with the TCP protocol (see the ticket).
In fact, the condition does not make sense for TCP, since after successful
connection to an upstream switching to another upstream never happens. As for
UDP, the issue with stuck buffers is unlikely to happen, but is still possible.
Specifically, if a filter delays sending data to upstream.
The condition can be relaxed to only check the "buffered" bitmask of the
upstream connection. The new condition is simpler and fixes the ticket issue
as well. Additionally, the upstream_out chain is now reset for UDP prior to
connecting to a new upstream to prevent repeating the client data twice.
author | Roman Arutyunyan <arut@nginx.com> |
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date | Mon, 11 Sep 2017 15:32:31 +0300 |
parents | d620f497c50f |
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rev | line source |
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561 | 1 |
2 /* | |
3 * Copyright (C) Igor Sysoev | |
4412 | 4 * Copyright (C) Nginx, Inc. |
561 | 5 */ |
6 | |
7 | |
8 /* | |
9 * The ppc assembler treats ";" as comment, so we have to use "\n". | |
10 * The minus in "bne-" is a hint for the branch prediction unit that | |
11 * this branch is unlikely to be taken. | |
12 * The "1b" means the nearest backward label "1" and the "1f" means | |
13 * the nearest forward label "1". | |
577 | 14 * |
561 | 15 * The "b" means that the base registers can be used only, i.e. |
16 * any register except r0. The r0 register always has a zero value and | |
17 * could not be used in "addi r0, r0, 1". | |
18 * The "=&b" means that no input registers can be used. | |
938 | 19 * |
20 * "sync" read and write barriers | |
21 * "isync" read barrier, is faster than "sync" | |
22 * "eieio" write barrier, is faster than "sync" | |
23 * "lwsync" write barrier, is faster than "eieio" on ppc64 | |
561 | 24 */ |
25 | |
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26 #if (NGX_PTR_SIZE == 8) |
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27 |
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28 static ngx_inline ngx_atomic_uint_t |
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29 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, |
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30 ngx_atomic_uint_t set) |
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31 { |
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32 ngx_atomic_uint_t res, temp; |
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33 |
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34 __asm__ volatile ( |
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35 |
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36 " li %0, 0 \n" /* preset "0" to "res" */ |
938 | 37 " lwsync \n" /* write barrier */ |
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38 "1: \n" |
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39 " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
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40 /* and store reservation */ |
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41 " cmpd %1, %3 \n" /* compare "temp" and "old" */ |
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42 " bne- 2f \n" /* not equal */ |
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43 " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
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44 /* is not cleared */ |
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45 " bne- 1b \n" /* the reservation was cleared */ |
938 | 46 " isync \n" /* read barrier */ |
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47 " li %0, 1 \n" /* set "1" to "res" */ |
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48 "2: \n" |
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49 |
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50 : "=&b" (res), "=&b" (temp) |
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51 : "b" (lock), "b" (old), "b" (set) |
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52 : "cc", "memory"); |
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53 |
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54 return res; |
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55 } |
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56 |
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57 |
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58 static ngx_inline ngx_atomic_int_t |
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59 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) |
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60 { |
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61 ngx_atomic_uint_t res, temp; |
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62 |
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63 __asm__ volatile ( |
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64 |
938 | 65 " lwsync \n" /* write barrier */ |
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66 "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */ |
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67 /* and store reservation */ |
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68 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ |
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69 " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ |
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70 /* is not cleared */ |
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71 " bne- 1b \n" /* try again if reservation was cleared */ |
938 | 72 " isync \n" /* read barrier */ |
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73 |
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74 : "=&b" (res), "=&b" (temp) |
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75 : "b" (value), "b" (add) |
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76 : "cc", "memory"); |
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77 |
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78 return res; |
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79 } |
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80 |
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81 |
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82 #if (NGX_SMP) |
938 | 83 #define ngx_memory_barrier() \ |
84 __asm__ volatile ("isync \n lwsync \n" ::: "memory") | |
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85 #else |
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86 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") |
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87 #endif |
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88 |
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89 #else |
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90 |
561 | 91 static ngx_inline ngx_atomic_uint_t |
92 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old, | |
93 ngx_atomic_uint_t set) | |
94 { | |
95 ngx_atomic_uint_t res, temp; | |
96 | |
97 __asm__ volatile ( | |
98 | |
99 " li %0, 0 \n" /* preset "0" to "res" */ | |
938 | 100 " eieio \n" /* write barrier */ |
937
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101 "1: \n" |
561 | 102 " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */ |
103 /* and store reservation */ | |
104 " cmpw %1, %3 \n" /* compare "temp" and "old" */ | |
937
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105 " bne- 2f \n" /* not equal */ |
561 | 106 " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */ |
107 /* is not cleared */ | |
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108 " bne- 1b \n" /* the reservation was cleared */ |
938 | 109 " isync \n" /* read barrier */ |
561 | 110 " li %0, 1 \n" /* set "1" to "res" */ |
937
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111 "2: \n" |
561 | 112 |
113 : "=&b" (res), "=&b" (temp) | |
114 : "b" (lock), "b" (old), "b" (set) | |
115 : "cc", "memory"); | |
116 | |
117 return res; | |
118 } | |
119 | |
120 | |
121 static ngx_inline ngx_atomic_int_t | |
122 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add) | |
123 { | |
124 ngx_atomic_uint_t res, temp; | |
125 | |
126 __asm__ volatile ( | |
127 | |
938 | 128 " eieio \n" /* write barrier */ |
561 | 129 "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */ |
130 /* and store reservation */ | |
131 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */ | |
132 " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */ | |
133 /* is not cleared */ | |
134 " bne- 1b \n" /* try again if reservation was cleared */ | |
938 | 135 " isync \n" /* read barrier */ |
561 | 136 |
137 : "=&b" (res), "=&b" (temp) | |
138 : "b" (value), "b" (add) | |
139 : "cc", "memory"); | |
140 | |
141 return res; | |
142 } | |
563 | 143 |
144 | |
145 #if (NGX_SMP) | |
938 | 146 #define ngx_memory_barrier() \ |
147 __asm__ volatile ("isync \n eieio \n" ::: "memory") | |
563 | 148 #else |
149 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory") | |
150 #endif | |
611 | 151 |
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152 #endif |
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153 |
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154 |
611 | 155 #define ngx_cpu_pause() |