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561
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1
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2 /*
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3 * Copyright (C) Igor Sysoev
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4 */
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5
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6
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7 #if (NGX_SMP)
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8 #define NGX_SMP_LOCK "lock;"
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9 #else
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10 #define NGX_SMP_LOCK
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11 #endif
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12
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13
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14 /*
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15 * "cmpxchgl r, [m]":
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16 *
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17 * if (eax == [m]) {
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18 * zf = 1;
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19 * [m] = r;
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20 * } else {
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21 * zf = 0;
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22 * eax = [m];
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23 * }
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24 *
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25 *
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26 * The "q" is any of the %eax, %ebx, %ecx, or %edx registers.
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27 * The "=a" and "a" are the %eax register. Although we can return result
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28 * in any register, we use %eax because it is used in cmpxchgl anyway.
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29 * The "cc" means that flags were changed.
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30 */
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31
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32 static ngx_inline ngx_atomic_uint_t
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33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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34 ngx_atomic_uint_t set)
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35 {
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36 ngx_atomic_uint_t res;
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37
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38 __asm__ volatile (
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39
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40 NGX_SMP_LOCK
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41 " cmpxchgl %3, %1; "
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42 " setz %b0; "
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43 " movzbl %b0, %0; "
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44
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45 : "=a" (res) : "m" (*lock), "a" (old), "q" (set) : "cc", "memory");
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46
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47 return res;
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48 }
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49
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50
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51 /*
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52 * "xaddl r, [m]":
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53 *
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54 * temp = [m];
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55 * [m] += r;
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56 * r = temp;
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57 *
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58 *
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59 * The "+q" is any of the %eax, %ebx, %ecx, or %edx registers.
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60 * The "cc" means that flags were changed.
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61 */
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62
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63
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64 #if !(__GNUC__ == 2 && __GNUC_MINOR__ <= 7)
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65
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66 static ngx_inline ngx_atomic_int_t
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67 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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68 {
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69 __asm__ volatile (
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70
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71 NGX_SMP_LOCK
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72 " xaddl %0, %1; "
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73
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74 : "+q" (add) : "m" (*value) : "cc", "memory");
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75
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76 return add;
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77 }
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78
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79
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80 #else /* (__GNUC__ == 2 && __GNUC_MINOR__ <= 7) */
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81
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82 /*
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83 * gcc 2.7 does not support "+q", so we have to use the fixed %eax ("=a" and
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84 * "a") and this adds two superfluous instructions in the end of code,
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85 * something like this: "mov %eax, %edx / mov %edx, %eax".
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86 */
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87
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88 static ngx_inline ngx_atomic_int_t
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89 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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90 {
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91 ngx_atomic_uint_t old;
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92
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93 __asm__ volatile (
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94
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95 NGX_SMP_LOCK
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96 " xaddl %2, %1; "
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97
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98 : "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");
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99
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100 return old;
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101 }
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102
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103 #endif
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